Re: [sv-bc] delays for strength changes

>From: "Jason Campbell" <jcampbell@winterlogic.com>

>I could not find anywhere in the specification where it states what delay
>should be selected for a strength change without a value change. This could
>happen through a mos primitive.

This is actually specified, though it may not be clear that it was
specified.  The table of propagation delays does not include this case,
but the textual description still applies.  From IEEE Std 1364-2005 7.14:

"For a three-delay specification,

 -- The first delay refers to the transition to the 1 value (rise delay).
 -- The second delay refers to the transition to the 0 value (fall delay).
 -- The third delay refers to the transition to the high-impedence value."
 
A strength transition without a value change is still a transition "to"
a 0 or 1 value, even if it is not "from" a different value.  The rule
specifies that it is the "to value" that matters in selecting the delay.
So a strength change that results in a value of 1 will use the first delay.
A strength change that results in a value of 0 will use the second delay.

I tested this in Verilog-XL, to determine the legacy behavior in this case.
It uses the first delay for a strength change with a value of 1, and the
second delay for a strength change with a value of 0, as the LRM text says.
NC-Verilog has followed this same behavior, and I assume that other
simulators have also (either to match Verilog-XL or the LRM text).

Steven Sharp
sharp@cadence.com


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