[sv-bc] RE: [sv-ec] [system-verilog] synthesis query for default value of bit type

In Verilog, a variable declaration assignment had to be a constant expression. I don't think the problem would exist with that restriction. There were reasons for relaxing the restriction, but the problem is due to a combination of factors, that is both the lack of order and allowing non-constant expressions.

Shalom

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From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Rich, Dave
Sent: Friday, January 23, 2009 7:14 PM
To: Prakash Barnwal; sv-bc@server.eda.org
Subject: [sv-bc] RE: [sv-ec] [system-verilog] synthesis query for default value of bit type

Moving this to the sv-bc, as this is the committee that handles design issues.

This is commonly known as the "static initialization order fiasco" in C/C++. See http://www.parashift.com/c++-faq-lite/ctors.html#faq-10.12. You cannot depend on the initialization order of static variables; they are not part of the procedural code. Some day, I would like to see an order defined within a local scope.

As far as considering the initial values of static variable for synthesis, that should be a tool/user decision. Some simulation tools have the ability to randomize the initial values, so effectively you could treat them as unknown.

Dave Rich
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