probably left over from Verilog. 1364 LRM ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Bresticker, Shalom Sent: Thursday, January 15, 2009 6:32 AM To: Daniel Mlynek; sv-bc@server.eda-stds.org Subject: RE: [sv-bc] output_terminal ::= net_lvalue 4.9.6 also says that primitive output terminals must be connected to nets, not variables. I don't know what the reason is. Shalom ________________________________ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Daniel Mlynek Sent: Thursday, January 15, 2009 4:11 PM To: sv-bc@server.eda-stds.org Subject: [sv-bc] output_terminal ::= net_lvalue LRM for gate instantation have : output_terminal ::= net_lvalue Above forbids to use variable on output ports - this is intentional restriction - or variables should be allowed on output gate terminals? DANiel -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 15 07:50:00 2009
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