[sv-bc] macro_text length limit?

In 1364-2005.pdf and P1800-2009 draft 8, I don't see any
mention of a limit to the number of characters in the
macro_text.  Is there such a limit?  Should there be one,
or some requirement that an implementation allow at least
some number?

(I found a GNU CPP document that mentions that
"The C standard requires a minimum of 4096 [characters
on a logical source line] be permitted."  It also mentions
the number of significant initial characters, number of
simultaneous macros, and number of arguments.)

There are some Verilog-AMS models that make extensive use
of macros for compact device models -- eg, an entire diode
model (with leakage, breakdown, capacitance, etc.) defined
as a macro so that it can be instantiated once for drain-
body and once for source-body.

-Geoffrey

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