[sv-bc] Question on mandatory "static" to declare intent

(Apologies if this comes too late)

I have a question from P1800/D8. Part of section 6.21 describes the
conditions under which use of the "static" keyword is mandatory to
confirm intent, where its use would otherwise be redundant.  In the
examples we have:

int svar1 = 1; // static keyword optional
initial begin
  int svar2 = 2; // static keyword optional
  ...

module top_illegal; // should not compile
initial begin
  for (int i=0; i<3; i++) begin
    int loop3 = 0; // illegal statement
    ...

The question: why is "static" optional on svar2? It will be optional
if it is illegal to declare svar2 as automatic. But I see no text
making it illegal to do so. In this example it's pointless, as one can
prove that an automatic svar2 would be initialized only once. But is
there any difference between:

initial begin
  int var1 = ...; // In theory static is optional
...
end

always begin
  int var2 = ...; // ???
  ...
  #10;
end

I might want to have var2 initialized each time through the "always"
block, and therefore I ought to declare it automatic. But is this not
the same situation as with the static block and var1?  At least two
commercial simulators accept automatic definitions inside both
"initial begin" and "always begin" blocks.

Interestingly, one of the tools I've tried accepts:

initial begin
  int i = 1;
...

But rejects:

always begin
  int i = 1;
...

From a usability standpoint I agree with the tool's decision to reject
the latter. However, that doesn't jibe with a literal interpretation
of the LRM text. Since it is not illegal to declare the variable as
automatic in either case (but in the "initial" case it may be
pointless) the "static" should be mandatory in both cases.

Perhaps the clause stating:

"The static keyword shall be optional where it would not be legal to declare the
variables as automatic"

should be reworded as:

"The static keyword shall be optional where the compiler can determine
that initialization can occur at most once regardless of the intended
lifetime of the variable."

And if this has to wait for Verilog-2012 then so be it.

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