>From: "Satyakam Sudershan" <satyakam@magma-da.com> > Wouldn't the normal Verilog semantics ensure that the once the >function variable are "copied" to the parent scope and the same >variables shared between different function calls; the problem of the >register not guaranteed to have the same value will also be handled? Yes. If the different callers are all using the same static function_temp variable, this will give the same effect as the function. If you can synthesize that, then you can presumably get the same behavior as with the function call. It is unlikely that this is the behavior the user actually wanted. It might be kinder to give them an error than to give them what they asked for. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Dec 10 10:13:10 2008
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