[sv-bc] Access using external names for unnamed generate blocks

Hi,

I have a query  regarding External names for unnamed generate blocks .
According to LRM IEEE Std 1364-2005 section 12.4.1 Loop generate constructs

"If the generate block is not named, the declarations within it cannot 
be referenced
using hierarchical names other than from within the hierarchy 
instantiated by the
generate block itself."

Is the testcase given below valid ?

module top(input clk);
integer dummy;
genvar i;
generate
 for(i=0; i<2; i=i+1) begin
   localparam tmp = 2;
 end
 wire [3:0] tmp2 ;
 assign tmp2 = genblk1[1].tmp;  // is this hierarchical reference valid
endgenerate

always @(clk)
 dummy = genblk1[1].tmp; // is this hierarchical reference valid

endmodule

Some standard tools are passing while others are giving the following 
error :
           "Implicit name not allowed in hierarchical name, 'genblk1[1]' "

Thanks,
Sarani



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