hi Cliff, SV-BC, > RTL models do not need a timescale as long as none of the models > compiled has a timescale or as long as the first model compiled has a > timescale. > I put a timescale in my testbench and compile it first. After that, > 0-delay RTL models compile just fine. That's a bit flaky in a separate-compilation flow, and doesn't help if the TB and its friends have timeunit/timeprecision within their modules. > (1) If the module has a delay, add a timescale in front of the module > - otherwise you are at compile-order mercy with other timescales in > the design. But isn't that precisely why SV's timeunit/timeprecision is such a good thing? Using that exclusively, and eschewing `timescale, means that I never need to worry about compilation order again (at least, not from the timescale point of view). -- Jonathan Bromley Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Nov 21 04:35:28 2008
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