Hooray! Thanks for the pointer. -- Matt Maidment mmaidmen@ichips.intel.com >-----Original Message----- >From: Bresticker, Shalom >Sent: Wednesday, October 15, 2008 10:40 PM >To: Maidment, Matthew R; sv-bc@eda.org >Cc: sv-ac@eda.org; sv-sc@eda.org >Subject: RE: [sv-bc] Packed dimension [0:0] - What should happen? > >11.5.1 (Draft 7a) says, > >"A bit-select or part-select of a scalar ... shall be illegal." > >Shalom > > >> The problem I have seen is related to identifiers declared as >> 1-bit scalars: >> >> reg foo; >> >> Some tools accept reference to foo as >> >> foo >> >> and >> >> foo[0:0] >> >> I believe the latter is an artifact of Verilog-XL. IMO, the >> latter should not be allowed. >> It was a "feature" of Verilog-XL and other tools that were >> written to comply. >> I don't believe it is described in a LRM. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Oct 15 23:09:20 2008
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