Re: [sv-bc] Mantis 1111, omitting range on port declaration

Following up to http://www.eda-stds.org/sv-bc/hm/6078.html ...

Is the following a legal port declaration? 

    input [5:0] in;
    bit [5:0] in;

or must they be combined?

    input var bit [5:0] in;

Also, is the following a legal port declaration?

    typedef logic [1:5] T;

    input [1:10] in;
    T [1:10] in; // 1 to 5 varies most rapidly

or must they be combined?

    input T [1:10] in;

-- Brad



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