[sv-bc] Query on multiply instantiated modules...

Hi there,

 

In the top level design "top", module "mid" is instantiated as below.

- - - - output logic dout;

- - - - mid i_mid [1:0] (

            .state_o(dout),

            -

            -

            -

            -

);

 

The above module is elaborated as,

mid \i_mid[0]  (

    .state_o(dout), 

      -

      -

      -

      -

);

 

mid \i_mid[1]  (

    .state_o(dout),

      -

      -

      -

      -

);

 

After elaboration, it looks like the signal "dout" is multiply driven
(from the output "state_o" of both the instantiations).

Would this be the correct behavior?

Or since "dout" is one bit, should some kind of truncation take place
and only the output "state_o" of module "\i_mid[0]" be connected to
dout?

 

Please let me know incase if there are any pointers on this in the LRM.

 

Thanks

-Anand

 


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