[sv-bc] RE: [sv-ec] Scope specific keyword

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Fri Jul 25 2008 - 02:40:54 PDT
Surya,

See 19.11 of IEEE Std 1364-2005, specifically, the "1364-2001-noconfig"
version specifier.

-- Brad


-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Surya Pratik Saha
Sent: Friday, July 25, 2008 5:16 PM
To: sv-ec@eda.org; sv-bc@eda.org
Subject: [sv-ec] Scope specific keyword

Hi,
Does SV or Verilog LRM define some keywords as scope specific? I did not

see any. But some of the standard simulators considers 'instance' as 
keyword inside 'config' scope only. In other places, you can use it as 
identifier. Though Verilog 1364-2005 LRM defines 'instance' in the 
keyword list. So following case should fail:

module top;
    integer instance;
endmodule

Please let me know it is the simulator bug or am I missing anything.

-- 
Regards
Surya




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Received on Fri Jul 25 02:42:49 2008

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