[sv-bc] Merge problem: T/F formal args - a proposal

In 13.3 (and similarly in 13.4):

The prose following the example "mytask2", concerning default direction and data_type
appears to apply only to "mytask1" - the ANSI-style tf_port list.  As is, it leaves
no way to declare local variables of a task or function.  Non-ANSI tf headers are
also under-defined: the positional ordering of their formal parameters are not given,
and the messy rules covering implicit and deferred type/direction vs formal uses
are simply not given - were they ever?

Please rearrange the text of these two nearly identical sections
that describe task/function arguments to say the following:
------------------------------------

13.x.1 Task formal arguments

A task declaration can specify formal arguments either in parentheses (like ANSI C):
      task mytask1 (output int x, input logic y);
          ...
      endtask

or in direction declarations with implicit, deferred, or explicit type declarations.
      task mytask2;
          output x;
          input y;
          int x;
          logic y;
          ...
      endtask

Each formal argument has one of the following directions:

          input               // copy value in at beginning
          output              // copy value out at end
          inout               // copy in at beginning and out at end
          ref                 // pass reference (see 13.5.2)

 >>> Insert
13.x.1.1  Verilog style

In Verilog-style tasks (functions), formal ports are introduced and given
their positional order by tf_port_declarations.  The tf_port_declaration
for a formal argument may be separated from a block_item_declaration
of the same name which specifies that formal's data_type, as in mytask2 above.
For maximum clarity, use one combined tf_port_declaration for each formal argument
or use an ANSI-C style parenthesized port list.

13.x.1.2 ANSI-C style

In an ANSI-C style tf_port_list, all names declared within the parentheses become
formal arguments - in the positional order of their declaration.  There is no merger
of type and direction information since each formal name may occur only once in any
tf_port_list.

<<< end insertion; the following paragraphs now live one section level deeper...

There is a default direction of input if no direction has been specified. Once a direction is given, subse-
quent formals default to the same direction. In the following example, the formal arguments a and b default
to inputs, and u and v are both outputs.

      task mytask3(a, b, output logic [15:0] u, v);
          ...
      endtask

Each formal argument also has a data type that can be explicitly declared or inherited from the previous
argument. a previous declaration. The task argument default type in SystemVerilog is logic if no type has
been specified. If the data type is not explicitly declared, then the default data type is logic if it is the first
argument or if the argument direction is explicitly specified. Otherwise the data type is inherited from the
previous argument.


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