RE: [sv-bc] merge error on timescale

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Sun Jun 01 2008 - 01:53:50 PDT
3.13.2.3 currently says, "It shall be an error if some design elements
have a time unit and precision specified and others do not."

"Design element" is defined in 3.2: "A design element is a SystemVerilog
module, program, interface, package, primitive or configuration." 

This implies that if timescales are used, then packages must also have a
timescale defined. Is that really so?

Shalom

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com] 
> Sent: Saturday, May 31, 2008 1:03 AM
> To: sharp@cadence.com; sv-bc@eda.org; Bresticker, Shalom
> Subject: RE: [sv-bc] merge error on timescale
> 
> 
> >From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> 
> >Not every compilation unit has to have a timescale defined. I don't 
> >think it is clear when it does and when it does not.
> 
> I assume that none of them are required to have it.  I see 
> problems with requiring it.
> 
> If a compilation unit is considered to exist even if there 
> are no declarations in it, then this would cause all legacy 
> Verilog designs containing `timescale to become illegal 
> SystemVerilog designs.  They would have a compilation unit 
> without a timescale, while the modules would have a timescale.
> 
> If a compilation unit is considered to exist only if there 
> are declarations in it, then legacy Verilog designs would be 
> fine.  However I assume that implementations have not been 
> enforcing this requirement, so it would not be backward 
> compatible with existing SystemVerilog designs.  They would 
> need timeunit and timeprecision constructs added in each 
> compilation unit to make them legal.
> 
> I also see problems with not requiring it.  Users are 
> accustomed to being able to put a `timescale in their first 
> file or at the start of all of their files, and have the 
> timescale set for everything.  But a `timescale has no effect 
> on compilation units (presumably because it is legal in 
> Verilog to have multiple different `timescale directives in 
> what became the compilation unit).  So any delays in tasks in 
> $unit will use the default timescale, even though the user 
> thought that they set the timescale for everything.  The same 
> applies to the scaling of $time in any tasks or functions in $unit.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
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Received on Sun Jun 1 01:55:48 2008

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