RE: [sv-bc] 22.2.2.2 port types

All ports must have a formally declared type. So effectively for a port
expression, the data type of the port is type(expr). What might not be
clear is that the kind of port, variable or net, is also inferred from
the expression. What's missing and probably much more difficult to
define than implement is all the rules for expressions for mixes of net,
variables, parameters and constants.

 

Once you have a formally defined data type and kind, all the rules of
22.3.3 apply, i.e. output ports must be legal lvalue types, inouts must
be nets, etc.

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Wednesday, April 16, 2008 5:18 AM
To: sv-bc
Subject: RE: [sv-bc] 22.2.2.2 port types

 

The same text also appears in 24.5.4.

 

Shalom

	 

	22.2.2.2 (ANSI style ports) says, 

	"The self-determined type of the port expression becomes the
type for the port. The port expression shall not be considered an
assignment-like context. The port expression must resolve to a legal
expression for type of module port (see 22.3.3). The port expression is
optional because ports can be defined that do not connect to anything
internal to the port."

	I don't understand this paragraph, especially the first and
third sentences. Can someone explain it to me? 

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