[sv-bc] Multidim array of interfaces - supported?

Hi,

 

I am little confused over array of interface construct in SV-2005 LRM.
It seems most of the standard tools/simulators supports one dimensional
array of interface; however they don't support multi-dimensional array
of interfaces. Does language prohibits that? I did not find any LRM
section/verse commenting on that. Can you suggest me what is per
standard?

 

Your suggestion is important to me.

 

Thanks,

Subhamoy

 

 

Example1 - (supported by standard tools/simulators)

========

interface ifc;

bit clk_in;

bit clk_out;

logic [7:0] data;

endinterface

 

module squat_1(ifc Rx[0:2]);

endmodule

 

module squat_2(ifc Tx);

endmodule

 

module test;

ifc Rx[0:2]();

ifc Tx();

squat_1 squat_1(Rx);

squat_2 squat_2(Tx);

endmodule

 

Example2 - (standard tools/simulators error out)

========

interface ifc;

bit clk_in;

bit clk_out;

logic [7:0] data;

endinterface

 

module squat_1(ifc Rx[0:2][0:2]);

endmodule

 

module squat_2(ifc Tx);

endmodule

 

module test;

ifc Rx[0:2][0:2]();

ifc Tx();

squat_1 squat_1(Rx);

squat_2 squat_2(Tx);

endmodule


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.