Re: [sv-bc] RE: [sv-ac] RE: [sv-ec] Checkers & Formal

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Mon Mar 10 2008 - 00:06:53 PDT
Korchemny, Dmitry wrote:
> Hi all,
> 
> I am attaching a presentation for tomorrow.
> 
> Thanks,
> Dmitry

I've taken a quick look at the slides.  You did deal with
at least one of the questions that I had outstanding -- what
is the meaning of forcing a checker variable?  You suggest
that it should be illegal.  Does that apply to all forms
of procedural continuous assignments to such a variable?
What about other assignments?  What would it mean, for
example, to have an NBA to or from a checker freevar?

What about use of a freevar on the RHS of a continuous
assignment?  For example:
    assign w = some_checker.some_freevar;
At what point does "some_freevar" change according to
the simulation cycle?  Is it even guaranteed to change?
Particularly for an unassigned freevar, it seems that
there is no requirement for the freevar to ever change.
How much simulator implementation variability is valid?

 From what I think I've heard, it seems unlikely to me that
inspecting or using a freevar value during simulation would
be terribly useful, particularly given the lack of
constraints on the implementation behavior in assigning to
the unassigned freevars.  Is that the case?  If so, should
all non-checker use of a freevar just be made illegal?
It might be more useful in terms of cross-vendor consistency
to define how simulators MUST select the values of unassigned
freevars.  Even something trivial like assigning them all
the value zero or possibly having a separate RNG that is
used.  Vendors could also extend things in other ways,
but having reasonably predictable cross-vendor behavior
would seem to be an important goal.

Gord.
-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Mon Mar 10 00:07:48 2008

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