Re: white space between tick and identifier (was Re: [Fwd: Re: [sv-bc] P1800-2008 draft 4 pg 526])

From: Steven Sharp <sharp_at_.....>
Date: Tue Mar 04 2008 - 17:17:59 PST
>I think that spaces between the tick and the identifier should be 
>allowed for at least two reasons.  First, backwards compatibility.  If 
>space between ticks and idents becomes illegal some designs will no 
>longer compile.

FWIW, Verilog-XL appears to allow white space between the tick and the
identifier, both for macro invocations and for compiler directives.  So
that does appear to be the de facto standard.

Steven Sharp
sharp@cadence.com


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Received on Tue Mar 4 17:18:34 2008

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