RE: [sv-bc] Checkers & Formal

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Tue Mar 04 2008 - 12:05:12 PST
Cliff,

What would the specific agenda of such a joint meeting be? 

That is, what are we going to decide?

-- Brad


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Clifford E. Cummings
Sent: Tuesday, March 04, 2008 11:49 AM
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-bc] Checkers & Formal

Thanks, Steven for distributing the slides.

The slides help but I think what we really need is to have a joint
meeting between the BC & EC and at least the following individuals from
the AC: Dimitry, Ed Cerny and Harry Foster. There are times when I
cannot tell if the slide is promoting a feature or discouraging a
feature.

I would like Dimitry to make the presentation (we don't need Webex or
anything, we can all follow the slides) and I would like to have two
very trusted Formal guys in Ed and Harry to help address questions. 
If Dimitry says something is "needed" I want to question Ed and Harry to
ask what the alternatives could be. I have a great deal of trust and
respect for the opinions of Ed and Harry, gained over many years of
interaction with them both.

Does this makes sense? Could we make this happen?

Otherwise, I would be inclined to vote the whole mess out and take it up
again in the next rev of 1800, along with some of the messes that I was
proposing.

Regards - Cliff

At 10:16 AM 3/4/2008, Steven Sharp wrote:
>I am attaching the PowerPoint presentation on checkers that Dmitry
sent.
>
>Steven Sharp
>sharp@cadence.com

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog,
SystemVerilog, Synthesis and Verification Training


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Received on Tue Mar 4 12:06:13 2008

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