RE: [sv-bc] Does `\'" violate V95 compatibility?

Greg,
   That is interesting.  There is a certain amount of backward
incompatibility that you would expect when you add new compiler
directives

For example this would be treated differently in V95 vs. V2001

`define ifndef $display("Hello World");

`ifndef foo
	$display("Hello");



So the LRM says "it shall be illegal to redefine a compiler directive as
a macro name."

So that would cover cases such as the one I gave above.
But you point out an interesting corner case.

I don't believe 

`define \`" 42

would trigger an error that you are re-defining an existing compiler
directive, since at the point where the macro is defined it would appear
to just be a normal escaped identifier.  Its not til you actually use it
that it appears to be a SV compiler directive with a special meaning. 
I was trying to think of any other cases where this same issue would
occur, but I didn't come up with any.  I think it might be a unique case
because any other macro name that started with \ would be treated as an
escaped identifier.

~Alex


-----Original Message-----
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Greg Jaxon
Sent: Monday, March 03, 2008 4:32 PM
To: SV_BC List
Subject: [sv-bc] Does `\'" violate V95 compatibility?

In Verilog it is legal to
`define \`"  42
You'd invoke this using `\`" , but according to P1800-2008 draft 4:

A `\`" indicates that the expansion should include the escape sequence
\".

Modifying their example slightly:
    `define msg(x,y) `"x: `\`" y`\`" `"
An example of using this `msg macro is:
    $display(`msg(left side,right side));
The example above expands to:
    $display("left side: \" right side\" ");

But under V95 it would have expanded to either:
    $display("left side: 42right side42");    or
    $display("left side: 42 right side 42 ");   depending on how token
gluing was treated.

I don't think it's a serious violation.
Is there a list of these nits?

Greg Jaxon



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