[sv-bc] RE: [sv-ec] LRM e.g. is wrong.

Surya, you are correct.
 
This is in 24.9.2 in Draft 4. The same error occurs in 24.5.5.
The latter is in Mantis 1541, but the second part of that Mantis has not
been addressed, so I will make sure that both of these typos are handled
by the editor, as well as update the Mantis.
 
Thanks,
Shalom


________________________________

	From: owner-sv-ec@server.eda.org
[mailto:owner-sv-ec@server.eda.org] On Behalf Of Surya Pratik Saha
	Sent: Wednesday, February 27, 2008 8:27 AM
	To: sv-ec@server.eda.org; sv-bc@server.eda.org
	Subject: [sv-ec] LRM e.g. is wrong.
	
	
	Hi,
	In 1800-2005 LRM section "20.8.2 Virtual interfaces modports and
clocking blocks", there is a big example of program using interface
port. In that example, there is a line 
	
	assert property (b1.p1); // assert property from within program
	
	Whereas, 'b1' is an interface port pointing to an instance,
which directly does not contain any object called 'p1'. Property 'p1' is
present inside a clocking block. All the standard simulators fail the
case. I am not sure if there is any mantis to fix it or not, but the
draft4 of 1800-2008 LRM does not contain any fix.
	
	-- 
	Regards
	Surya

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