Re: [sv-bc] Hierarchical reference within packages

I consider both cases to be legal -- the A_I.c reference
is not "hierarchical" but is a reference through a
virtual interface variable.  If that wouldn't be legal,
it would pretty much kill the usefulness of virtual interfaces.

In the second case, you should run into a different
issue.  Since the task "t" is static, the variable "x" is
also static and will be initialized to A_I.c *before* the
first call.  That means that A_I (which is also static)
will be null and you should see some sort of error.  Making
the task automatic or moving the assignment of
x = A_I.c into the body would resolve that issue.

Gord.


Alok Kumar Sinha wrote:
> Hi
> 
> As the LRM restricts the reference of outer package items within a 
> package or compilation unit scope, are the following cases
> legal in which hierarchical references are used as shown .
> 
> Consider the following cases :
> Case 1:
>  interface A;
>  bit c;
> endinterface
> 
> class C;
>     virtual A A_I;
>     function new (virtual A A_I1);
>         A_I = A_I1;
>     endfunction
> 
>     task t;
>      forever begin
>                 @(posedge A_I.c)    // 'c' is declared within interface 'A'
>                 $display("");
>             end
>     endtask
> endclass
> 
> module top;
>     A A_I();
>     initial
>         begin
>          C CObj = new(A_I);
>          CObj.t;
>         end
> endmodule
> 
> Case 2:
> 
> interface A;
>     bit c;
> endinterface
> 
> task t(virtual A A_I);
> bit x = A_I.c;    // 'c' is declared within interface 'A'
> endtask
> module top;
> A A_I();
> initial begin
>     t(A_I);
> end
> endmodule
> 
> It is to be noted that some tools passes the first case and fails on second.
> Can anyone please clarify it.
> 
> Regards
> Alok
> 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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