RE: [sv-bc] Query for sysytem function $clog2

Sumay,

See http://www.eda-stds.org/sv-bc/hm/7947.html .

-- Brad 

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Sumay Guin
Sent: Tuesday, February 19, 2008 11:35 PM
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-bc] Query for sysytem function $clog2

Hi,
Though $clog2 is not a SV specific function, but I am not sure where
should I ask my quaries. So I am using SV-BC alias. If it is not proper
body to discuss then please let me know.

verilog LRM 1364-2005 section 17.11.1 says  that " This ( $clog2 )
system function can be used to compute the minimum address width
necessary to address a memory of a given size or the minimum vector
width necessary to represent a given number of states".
 
Consider the scenario,
      
       module Top;
        localparam b = $clog2(-1); // is the result 32  ?
        localparam c = $clog2(1);  //  is the result 1  ?
        localparam d = $clog2(100); // is the result 7 ?
        localparam e = $clog2(32); //  is the result 5  ? though no. of
bits to represent 32 is 6
       endmodule
   
Stanandard simulator behaviour is conflictiing and confusing for the
case. For e.g. some of them giving 6 for $clog2(32). What is the corret
result?

  Thanks regrards
   Sumay   



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