RE: [sv-bc] input port kind

Hi,
 
We discussed this in Mantis 1984.
It should be illegal.
In reality, some tools allow it. 
One, for example, defines it as a wire with two-state semantics of their
own devising.
 
Shalom


________________________________

	From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of danielm
	Sent: Monday, February 18, 2008 12:38 PM
	To: 'sv-bc'
	Subject: [sv-bc] input port kind
	
	
	As per LRM 1800-2005:
	"For input and inout ports, if the port kind is omitted, then
the port shall default to a net of net type wire. This default net type
can be changed using the `default_nettype compiler directive, as in
Verilog."

	so inputs in below codes have kind as described below

	module sub(input reg i);//i is a net 

	endmodule

	 

	module sub(input var reg i); //i is a variable of type reg

	endmodule

	 

	module sub(input bit i);

	//what is kind of i in this case - i cannot be a net becouse
nets cannot have 2-value type. it shouold be an error? or i should be a
variable????? LRM doesnt specufy that.

	endmodule

	 

	 

	DANiel


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