> Another complication on this is a case like the following: > > always @(posedge clk or posedge rst) > if (rst) > q[2:0] <= 0; > else begin > q[2] <= in2; > q[0} <= in0; > end [...] > So should always_ff flag an error in such a case? Since this is my personal second most frequent design mistake (just behind the opposite one, resetting some but not all of the registers) I would quite like to see the warning (error?). I can easily suppress it with a tweak that is completely harmless, and odd enough to be almost self-documenting: always @(posedge clk or posedge rst) if (rst) q[2:0] <= 0; else begin q <= q; // suppress warnings about unclocked // registers with a reset q[2] <= in2; q[0} <= in0; end -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Feb 13 09:22:10 2008
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