Re: [sv-bc] Mantis 1984

Following up to 

   http://www.eda-stds.org/sv-bc/hm/7774.html

In the following example, only the first assignment is legal?


module test(input logic A, input logic B, input var C, D );
  assign A = 0;  // legal
  always @* begin
      B = A ;    // illegal to procedurally assign to wire
      C = A ;    // illegal to assign to input variable
  end
  assign D = 0;  // illegal to assign to input variable
endmodule


-- Brad


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