[sv-bc] RE: [sv-ec] 'reg' after net type

The reason for the restriction was to prevent typographical errors that
would be very difficult to detect the difference between

 

tri reg

 

and

 

trireg

 

It also is to encourage people to use logic instead of reg as a data
type because wire reg is visually contradictory to anyone familiar with
Verilog.

 

Dave

 

 

________________________________

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Surya Pratik Saha
Sent: Monday, December 17, 2007 10:20 PM
To: sv-ec@server.eda.org; sv-bc@server.eda.org
Subject: [sv-ec] 'reg' after net type

 

Hi,
As per SV LRM (6.6 Net declarations draft 4), following text is
mentioned:

A lexical restriction applies to the use of the reg keyword in a net or
port declaration. A net type keyword shall not be followed directly by
the reg keyword. Thus, the following declarations are in error:

Is there special meaning for that restriction. If 'wire scalared reg' is
allowed why then 'wire reg' is not allowed. Some tools pass 'wire reg r'
syntax. 



-- 
Regards
Surya

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