RE: [sv-bc] Mantis 1573

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Sat Dec 15 2007 - 15:02:18 PST
-----Bounced mail from Gord-----
Date: Sat, 15 Dec 2007 12:09:43 -0800

I'm not opposed to not mentioning collapsing -- I am opposed to saying
that one "shall" report a port direction waring if the implementation
doesn't coerce.  As long as no one claims that a collapsing
(non-coercing) implementation is required to warn, I am fine.

My basic concern is that either collapsing or coercion is fine;
attaching a *required* warning to be absence of coercion is
objectionable only if someone would then claim that a collapsing
implementation must warn.

I agree with Steven that "it can be thought of as"
a result of collapsing.

Gord.

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
Sent: Sat 12/15/2007 10:36 AM
To: Vreugdenhil, Gordon
Cc: sv-bc
Subject: RE: [sv-bc] Mantis 1573
=20
Gord,

I'm very disappointed that you and Steven seem to have incompatible
positions. You are opposed to not mentioning collapsing in addition to
coercion and he is opposed to mentioning collapsing in the context of
coercion.

Note that the current LRM text on coercion also does not mention
collapsing in the context of coercion. I don't think my proposed text
changes anything on the relationship between them.

Since you also said that you don't have a problem with the existing
text, your two positions seem inconsistent to me.

I understood Steven to mean, among other things, that coercion can be
thought of as a result of collapsing, so that coercion includes
collapsing.

I don't object to your proposed rewording. I just want you two to find a
mutually acceptable compromise so that it can more easily pass at the
Champions' level as well. Failing that, I'll accept whatever will pass
SV-BC with the fewest objections.

Regards,
Shalom=20

> -----Original Message-----
> From: owner-sv-bc@server.eda.org=20
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Gordon Vreugdenhil
> Sent: Friday, December 14, 2007 4:58 PM
> To: Bresticker, Shalom
> Cc: sv-bc
> Subject: Re: [sv-bc] Mantis 1573
>=20
> Shalom, this one I will object to.
>=20
> You have:
>     If not coerced to inout, a warning shall be issued. If=20  
>coercion does
>     not occur, the additional assignment to the signal sink=20  
>occurs, but
>     the port direction is preserved and the assignment does=20  not 
>pass through
>     the port connection to the signal source.
>=20
> This does not allow for a collapsing approach since you have:
>     "If coercion does not occur..."
>=20
> At the very least this must be something like, "If an=20  
>implementation neither coerces such a port nor collapses it,=20  the 
>addiitonal...."
>=20
> Gord.
>=20
> Bresticker, Shalom wrote:
> > I have uploaded yet another version of this.
> >=20
> > Shalom
> >=20
> >> -----Original Message-----
> >> From: Bresticker, Shalom
> >> Sent: Friday, December 14, 2007 11:34 AM
> >> To: sv-bc
> >> Subject: RE: [sv-bc] Mantis 1573
> >>
> >> I want to emphasize again that the original purpose of=20
> this Mantis is=20
> >> to clarify what is meant by "an input(output) used as an=20 
> >> output(input)" in its most common form (not PLI or hierarchical=20
> >> reference) and what is the behavior if coercion does not occur.
> >>
> >> The phrase has very frequently been misunderstood, even by=20
> committee=20
> >> members, and the behavior if coercion does not occur is 
> >> completely=20 unspecified by the LRM.
> >>
> >> So from the point of view of users, this issue is important.
> >>
> >> I'm going to make another try at wordsmithing this proposal.
> >>
> >> Shalom
> >=20
> ---------------------------------------------------------------------
> > Intel Israel (74) Limited
> >=20
> > This e-mail and any attachments may contain confidential=20
> material for=20
> > the sole use of the intended recipient(s). Any review or=20
> distribution=20
> > by others is strictly prohibited. If you are not the intended=20  
> >recipient, please contact the sender and delete all copies.
> >=20
> >=20
> >=20
> >=20
> ----------------------------------------------------------------------
> > --
> >=20
> > Mantis 1573
> >=20
> > P1800-2008/D4, 22.3.3.1
> >=20
> > Clarify input used as output and vice-versa =20  CHANGE =20
> > *22.3.3.1 Port coercion*
> >=20
> > A port that is declared as input (output) but used as an output=20
> > (input) or inout may be coerced to inout. If not coerced to=20
> inout, a=20
> > warning shall be issued.
> >=20
> >=20=20
> >=20
> > TO
> >=20
> > *22.3.3.1 Port coercion*
> >=20
> > A port that is declared as input (output) but used as an output=20
> > (input) or inout may be coerced to inout. If not coerced to=20
> inout, a=20
> > warning shall be issued.
> >=20
> >=20=20
> >=20
> >=20=20
> >=20
> >=20=20
> >=20
> > CHANGE
> >=20
> > *22.3.3.7 Port connections with dissimilar net types (net and port
> > collapsing)*
> >=20
> > * *
> >=20
> > *TO*
> >=20
> > *22.3.3.76** Port** connections with dissimilar net types (net 
> >and=20  port
> > collapsing)*
> >=20
> >=20=20
> >=20
> >=20=20
> >=20
> > ADD NEW
> >=20
> > *22.3.3.7 Port coercion*
> >=20
> >=20=20
> >=20
> > When both sides of an input or output port are nets and there is 
> >an=20  additional assignment to the port connection signal sink other

> >than=20  through the port connection (i.e., input port used as an 
> >output or=20  output port used as an input), the port may be coerced 
> >to inout. If=20  not coerced to inout, a warning shall be issued. 
> >If=20
> coercion does not=20
> > occur, the additional assignment to the signal sink occurs, but 
> > the=20 port direction is preserved and the assignment does not=20
> pass through=20
> > the port connection to the signal source.
> >=20
> >=20=20
> >=20
> > Example of an input port used as an output and of an output=20
> port used=20
> > as an input:
> >=20
> >=20=20
> >=20
> > *module* top ;
> >=20
> > *wire* in1, out1 ;
> >=20
> > m m(in1, out1);
> >=20
> > *assign* out1 =3D 1'b1;
> >=20
> > *endmodule***
> >=20
> >=20=20
> >=20
> >=20=20
> >=20
> > *module* m (in1, out1) ;
> >=20
> > *input* in1 ;
> >=20
> > *output* out1;        // out1 is driven outside the module=20
> and thus used=20
> > as an input
> >=20
> > *assign* in1 =3D 1'b0 ; // in1 is driven within the module=20
> and thus used=20
> > as an output
> >=20
> > *endmodule***
> >=20
> >=20=20
> >=20
>=20
> --
> --------------------------------------------------------------------
> Gordon Vreugdenhil                                503-685-0808
> Model Technology (Mentor Graphics)                gordonv@model.com
>=20
>=20
> --=20
> This message has been scanned for viruses and  dangerous content by 
>MailScanner, and is  believed to be clean.
>=20
>=20
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution by
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<P><FONT SIZE=3D2>I'm not opposed to not mentioning collapsing -- I
am<BR> opposed to saying that one &quot;shall&quot; report a port
direction<BR> waring if the implementation doesn't coerce.&nbsp; As
long<BR> as no one claims that a collapsing (non-coercing)<BR>
implementation is required to warn, I am fine.&nbsp;<BR> <BR> My basic
concern is that either collapsing or coercion<BR> is fine; attaching a
*required* warning to be absence<BR> of coercion is objectionable only
if someone would<BR> then claim that a collapsing implementation must
warn.<BR> <BR> I agree with Steven that &quot;it can be thought of
as&quot;<BR> a result of collapsing.<BR> <BR> Gord.<BR> <BR>
-----Original Message-----<BR>
From: Bresticker, Shalom [<A
HREF=3D"mailto:shalom.bresticker@intel.com">ma=
ilto:shalom.bresticker@intel.com</A>]<BR>
Sent: Sat 12/15/2007 10:36 AM<BR>
To: Vreugdenhil, Gordon<BR>
Cc: sv-bc<BR>
Subject: RE: [sv-bc] Mantis 1573<BR>
<BR>
Gord,<BR>
<BR>
I'm very disappointed that you and Steven seem to have incompatible<BR>
positions. You are opposed to not mentioning collapsing in addition
to<BR> coercion and he is opposed to mentioning collapsing in the
context of<BR> coercion.<BR> <BR> Note that the current LRM text on
coercion also does not mention<BR> collapsing in the context of
coercion. I don't think my proposed text<BR> changes anything on the
relationship between them.<BR> <BR> Since you also said that you don't
have a problem with the existing<BR> text, your two positions seem
inconsistent to me.<BR> <BR> I understood Steven to mean, among other
things, that coercion can be<BR> thought of as a result of collapsing,
so that coercion includes<BR> collapsing.<BR> <BR> I don't object to
your proposed rewording. I just want you two to find a<BR> mutually
acceptable compromise so that it can more easily pass at the<BR>
Champions' level as well. Failing that, I'll accept whatever will
pass<BR> SV-BC with the fewest objections.<BR> <BR> Regards,<BR>
Shalom<BR> <BR> &gt; -----Original Message-----<BR> &gt; From:
owner-sv-bc@server.eda.org<BR> &gt; [<A
HREF=3D"mailto:owner-sv-bc@server.eda.org">mailto:owner-sv-bc@serv=
er.eda.org</A>] On Behalf Of Gordon Vreugdenhil<BR> &gt; Sent: Friday,
December 14, 2007 4:58 PM<BR> &gt; To: Bresticker, Shalom<BR> &gt; Cc:
sv-bc<BR> &gt; Subject: Re: [sv-bc] Mantis 1573<BR> &gt;<BR> &gt;
Shalom, this one I will object to.<BR> &gt;<BR> &gt; You have:<BR>
&gt;&nbsp;&nbsp;&nbsp;&nbsp; If not coerced to inout, a warning shall be
is= sued. If<BR> &gt; coercion does<BR> &gt;&nbsp;&nbsp;&nbsp;&nbsp; not
occur, the additional assignment to the si= gnal sink<BR> &gt; occurs,
but<BR> &gt;&nbsp;&nbsp;&nbsp;&nbsp; the port direction is preserved and
the assign= ment does<BR> &gt; not pass through<BR>
&gt;&nbsp;&nbsp;&nbsp;&nbsp; the port connection to the signal
source.<BR> &gt;<BR> &gt; This does not allow for a collapsing approach
since you have:<BR> &gt;&nbsp;&nbsp;&nbsp;&nbsp; &quot;If coercion does
not occur...&quot;<BR> &gt;<BR> &gt; At the very least this must be
something like, &quot;If an<BR> &gt; implementation neither coerces such
a port nor collapses it,<BR> &gt; the addiitonal....&quot;<BR> &gt;<BR>
&gt; Gord.<BR> &gt;<BR> &gt; Bresticker, Shalom wrote:<BR> &gt; &gt; I
have uploaded yet another version of this.<BR> &gt; &gt;<BR> &gt; &gt;
Shalom<BR> &gt; &gt;<BR> &gt; &gt;&gt; -----Original Message-----<BR>
&gt; &gt;&gt; From: Bresticker, Shalom<BR> &gt; &gt;&gt; Sent: Friday,
December 14, 2007 11:34 AM<BR> &gt; &gt;&gt; To: sv-bc<BR> &gt; &gt;&gt;
Subject: RE: [sv-bc] Mantis 1573<BR> &gt; &gt;&gt;<BR> &gt; &gt;&gt; I
want to emphasize again that the original purpose of<BR> &gt; this
Mantis is<BR> &gt; &gt;&gt; to clarify what is meant by &quot;an
input(output) used as an= <BR> &gt; &gt;&gt; output(input)&quot; in its
most common form (not PLI or hiera= rchical<BR> &gt; &gt;&gt; reference)
and what is the behavior if coercion does not occu= r.<BR> &gt;
&gt;&gt;<BR> &gt; &gt;&gt; The phrase has very frequently been
misunderstood, even by<BR> &gt; committee<BR> &gt; &gt;&gt; members, and
the behavior if coercion does not occur is compl= etely<BR> &gt;
&gt;&gt; unspecified by the LRM.<BR> &gt; &gt;&gt;<BR> &gt; &gt;&gt; So
from the point of view of users, this issue is important.<=
BR>
&gt; &gt;&gt;<BR>
&gt; &gt;&gt; I'm going to make another try at wordsmithing this
proposal.<=
BR>
&gt; &gt;&gt;<BR>
&gt; &gt;&gt; Shalom<BR>
&gt; &gt;<BR>
&gt;
---------------------------------------------------------------------<=
BR>
&gt; &gt; Intel Israel (74) Limited<BR>
&gt; &gt;<BR>
&gt; &gt; This e-mail and any attachments may contain confidential<BR>
&gt; material for<BR> &gt; &gt; the sole use of the intended
recipient(s). Any review or<BR> &gt; distribution<BR> &gt; &gt; by
others is strictly prohibited. If you are not the intended<BR> &gt; &gt;
recipient, please contact the sender and delete all copies.<BR> &gt;
&gt;<BR> &gt; &gt;<BR> &gt; &gt;<BR> &gt; &gt;<BR> &gt;
----------------------------------------------------------------------=
<BR>
&gt; &gt; --<BR>
&gt; &gt;<BR>
&gt; &gt; Mantis 1573<BR>
&gt; &gt;<BR>
&gt; &gt; P1800-2008/D4, 22.3.3.1<BR>
&gt; &gt;<BR>
&gt; &gt; Clarify input used as output and vice-versa<BR> &gt; &gt;<BR>
&gt; &gt; CHANGE<BR> &gt; &gt;<BR> &gt; &gt; *22.3.3.1 Port
coercion*<BR> &gt; &gt;<BR> &gt; &gt; A port that is declared as input
(output) but used as an output<B=
R>
&gt; &gt; (input) or inout may be coerced to inout. If not coerced
to<BR> &gt; inout, a<BR> &gt; &gt; warning shall be issued.<BR> &gt;
&gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt; TO<BR> &gt;
&gt;<BR> &gt; &gt; *22.3.3.1 Port coercion*<BR> &gt; &gt;<BR> &gt; &gt;
A port that is declared as input (output) but used as an output<B=
R>
&gt; &gt; (input) or inout may be coerced to inout. If not coerced
to<BR> &gt; inout, a<BR> &gt; &gt; warning shall be issued.<BR> &gt;
&gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt;&nbsp;<BR> &gt;
&gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt; CHANGE<BR> &gt;
&gt;<BR> &gt; &gt; *22.3.3.7 Port connections with dissimilar net types
(net and por= t<BR> &gt; &gt; collapsing)*<BR> &gt; &gt;<BR> &gt; &gt; *
*<BR> &gt; &gt;<BR> &gt; &gt; *TO*<BR> &gt; &gt;<BR> &gt; &gt;
*22.3.3.76** Port** connections with dissimilar net types (net an= d<BR>
&gt; &gt; port<BR> &gt; &gt; collapsing)*<BR> &gt; &gt;<BR> &gt;
&gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt;
ADD NEW<BR> &gt; &gt;<BR> &gt; &gt; *22.3.3.7 Port coercion*<BR> &gt;
&gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt; When both sides of
an input or output port are nets and there is = an<BR> &gt; &gt;
additional assignment to the port connection signal sink other th=
an<BR> &gt; &gt; through the port connection (i.e., input port used as
an output o= r<BR> &gt; &gt; output port used as an input), the port may
be coerced to inout. = If<BR> &gt; &gt; not coerced to inout, a warning
shall be issued. If<BR> &gt; coercion does not<BR> &gt; &gt; occur, the
additional assignment to the signal sink occurs, but t= he<BR> &gt; &gt;
port direction is preserved and the assignment does not<BR> &gt; pass
through<BR> &gt; &gt; the port connection to the signal source.<BR> &gt;
&gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt; Example of an input
port used as an output and of an output<BR> &gt; port used<BR> &gt; &gt;
as an input:<BR> &gt; &gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt;
&gt; *module* top ;<BR> &gt; &gt;<BR> &gt; &gt; *wire* in1, out1 ;<BR>
&gt; &gt;<BR> &gt; &gt; m m(in1, out1);<BR> &gt; &gt;<BR> &gt; &gt;
*assign* out1 =3D 1'b1;<BR> &gt; &gt;<BR> &gt; &gt; *endmodule***<BR>
&gt; &gt;<BR> &gt; &gt;&nbsp;<BR> &gt; &gt;<BR> &gt; &gt;&nbsp;<BR> &gt;
&gt;<BR> &gt; &gt; *module* m (in1, out1) ;<BR> &gt; &gt;<BR> &gt; &gt;
*input* in1 ;<BR> &gt; &gt;<BR> &gt; &gt; *output*
out1;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; // out1 = is driven
outside the module<BR> &gt; and thus used<BR> &gt; &gt; as an input<BR>
&gt; &gt;<BR> &gt; &gt; *assign* in1 =3D 1'b0 ; // in1 is driven within
the module<BR> &gt; and thus used<BR> &gt; &gt; as an output<BR> &gt;
&gt;<BR> &gt; &gt; *endmodule***<BR> &gt; &gt;<BR> &gt; &gt;&nbsp;<BR>
&gt; &gt;<BR> &gt;<BR> &gt; --<BR> &gt;
--------------------------------------------------------------------<B=
R>
&gt; Gordon
Vreugdenhil&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs
p;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
503-685-0808<BR> &gt; Model Technology (Mentor
Graphics)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
gordonv@model.com<BR> &gt;<BR> &gt;<BR> &gt; --<BR> &gt; This message
has been scanned for viruses and<BR> &gt; dangerous content by
MailScanner, and is<BR> &gt; believed to be clean.<BR> &gt;<BR> &gt;<BR>
---------------------------------------------------------------------<BR
>
Intel Israel (74) Limited<BR>
<BR>
This e-mail and any attachments may contain confidential material
for<BR> the sole use of the intended recipient(s). Any review or
distribution<BR> by others is strictly prohibited. If you are not the
intended<BR> recipient, please contact the sender and delete all
copies.<BR> <BR> <BR> </FONT> </P>

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