RE: [sv-bc] Mantis 1984

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Sat Dec 15 2007 - 10:58:19 PST
That's the issue on 2-state datatypes for nets. I think that issue might
require more time than we have now. 
 
Shalom


________________________________

	From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
	Sent: Saturday, December 15, 2007 8:37 PM
	To: sv-bc
	Subject: RE: [sv-bc] Mantis 1984
	
	
	Then we should finally address ballot issue 228
	 
	     http://www.eda-stds.org/svdb/view.php?id=694
	 
	Back in 2005 I voted against deferring this issue.
	 
	-- Brad

________________________________

	From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf
Of Bresticker, Shalom
	Sent: Saturday, December 15, 2007 10:23 AM
	To: Brad Pierce; sv-bc
	Subject: RE: [sv-bc] Mantis 1984
	
	
	They should have been.
	 
	In 1800-2005, 19.8 says 
	 
	For input and inout ports, if the port kind is omitted, then the
port shall default to a net of net type wire.

	This default net type can be changed using the `default_nettype
compiler directive, as in Verilog.

	// the inout port defaults to a net of net type wire

	module mh2 (inout integer a);

	...

	endmodule

	That passage still exists in Draft 4 of P1800-2008.
	 
	Shalom
	 
	 
	 


________________________________

		From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
		Sent: Saturday, December 15, 2007 8:17 PM
		To: sv-bc
		Subject: RE: [sv-bc] Mantis 1984
		
		
		Shalom,
		 
		Are you saying that port declarations like
		 
		   module test(input int i, output o);
		   endmodule
		
		were illegal in IEEE Std 1800-2005? 
		 
		Do any existing tools really error on this?
		 
		-- Brad
		 
		 

________________________________

		From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]
On Behalf Of Bresticker, Shalom
		Sent: Saturday, December 15, 2007 9:59 AM
		To: Bresticker, Shalom; sv-bc
		Subject: RE: [sv-bc] Mantis 1984
		
		
		I revised the proposal by listing all the 'input bit'
cases.
		 
		Shalom


________________________________

			From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of Bresticker, Shalom
			Sent: Friday, December 14, 2007 1:10 PM
			To: sv-bc
			Subject: [sv-bc] Mantis 1984
			
			

			Please review above proposal. I would like to
vote on it on Monday. 

			Thanks, <<1984_D4_inputs.htm>> 
			Shalom 

			Shalom Bresticker 
			Intel Jerusalem LAD DA 
			+972 2 589-6582 
			+972 54 721-1033 

	
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Received on Sat Dec 15 11:04:42 2007

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