RE: [sv-bc] Packed arrays of bytes -- are they legal?

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Thu Dec 13 2007 - 01:21:36 PST
And can there be multiple continuous assignments or a mixture of
procedural and continuous assignments to different bits of such a
variable? I would think that the answer is yes.

See also Manti 1520 and 1595.

Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce
> Sent: Tuesday, December 11, 2007 5:36 PM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] Packed arrays of bytes -- are they legal?
> 
> Is the following illegal?
> 
>         typedef byte T1 ;
>         typedef T1 [3:0] T2 ;
> 
> According to 5.2 of IEEE Std 1800-2005
>  
>     "Packed arrays can be made of only the single bit data 
> types (bit, logic, reg) and recursively other packed arrays 
> and packed structures." 
> 
> and 
> 
>     "Although an integer type with a predefined width n is 
> not a packed array, it matches (see 6.9.2), and can be 
> selected from as if it were, a packed array type with a 
> single [n-1:0] dimension."
> 
> But a friend claims that this LRM restriction only prohibits 
> the byte, integer, shortint keywords from being used directly 
> in a packed array declaration.
> 
> An argument in favor of that viewpoint is 6.9
> 
>     "SystemVerilog does not require a category for identical 
> types to be defined here because there is no construct in the 
> SystemVerilog language that requires it. For example, as 
> defined below, int can be interchanged with bit signed [31:0] 
> wherever it is syntactically legal to do so.
> Users can define their own level of type identity by using 
> the $typename system function (see 22.2) or through use of the PLI."
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Received on Thu Dec 13 02:18:00 2007

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