[sv-bc] RE: [sv-ec] Is interface ref variable automatic?

This example is legal. Section 12.4.2 is talking about ref arguments
to tasks and functions. In your example you have a ref port on an
interface. You cannot attach a automatic variable to a ref port of
a module, interface or program, so no such restriction exists for
ref ports. 

> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On 
> Behalf Of Surya Pratik Saha
> Sent: Wednesday, December 12, 2007 12:43 AM
> To: sv-bc@eda.org; sv-ec@eda.org
> Cc: Adhip Das
> Subject: [sv-ec] Is interface ref variable automatic?
> 
> Hi,
> 
> Consider the following testcase,
> 
> interface intf (ref bit [3:0] ba);
> endinterface
> 
> module named1 ();
>    bit [3:0] ba;
>    assign o1 =  i2.ba;
>    intf i2 (ba);
> endmodule
> 
> As per systemverilog LRM 1800-2005, section 12.4.2 Pass by reference:
> 
> "Because a variable passed by reference may be an automatic 
> variable, a ref argument shall not be used in any context 
> forbidden for automatic variables."
> 
> Could you please tell me whether the above testcase is 
> erroneous or not?
> I guess, it is erroneous because ref variable(which should be 
> treated as automatic variable) is hierarchically referred(i2.ba).
> 
> --
> Regards
> Surya
> 
> 
> 
> 
> 
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