RE: [sv-bc] Macro mantis proposals 1397 & 1478

From: Brad Pierce <Brad.Pierce_at_.....>
Date: Wed Dec 05 2007 - 18:30:05 PST
> Mantis 1339 has been approved which adds the last sentence below:

Mantis 1339 is still being considered by the current e-mail vote.  Also,
I added the following bugnote to it

--------------------------

It would be nice to see an example of what this proposal means for macro
texts that end with escaped identifiers. For example, I think the
following would be legal Verilog under this proposal

   `define MAC(ignored) \!@#
   wire `MAC(ignored)%^&* = 1'b1;
   wire w = \!@#%^&* ; 

-------------------------

-- Brad

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Received on Wed Dec 5 18:30:24 2007

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