[sv-bc] Re: Referring into generate scope via interface port

As asked in

  http://www.eda-stds.org/svdb/view.php?id=1611
<http://www.eda-stds.org/svdb/view.php?id=1611> 

When an interface is passed through a module port without using a
modport, is it legal to refer into the generate scopes of the interface?

For example, if GEN[5] is a generate scope in the interface and 'sig' is
a wire declared within that scope, can I use an interface port 'ifc' of
a module to get at that wire?

     assign ifc.GEN[5].sig = 1'b0;

Apparently, I cannot list generated signals in a modport without using
the modport expression syntax. According to Syntax 20-1 the following is
not legal

    modport mp(input GEN[5].sig);

and I am forced to do

    modport mp(input .\GEN[5].sig (GEN[5].sig));

Is the BNF correct, or is it just trying to prevent passing out
hierarchical references or fields of a struct without a modport
expression, while forgetting about the possibility of generated signals?

If the BNF is correct, and I pass a modport instead of a naked
interface, then there's suddenly no way to say

   assign ifc.GEN[5].sig = 1'b0;

and I am forced to use modport expressions

   assign ifc.\GEN[5].sig = 1'b0;

I think the BNF for modport declarations is wrong, because a generated
modport can already provide access to a generated signal, without using
a modport expression, if they are both in the same generate block.

   interface intf_t #(num_clients = 0);
     //...
     for (genvar i=0; i< num_clients; i++) begin: mps
        bit req;
        modport client_mp (output req);
     end
     //...
   endinterface


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