RE: [sv-ac] Re: [sv-bc] Re: if-else

Has anyone come up with a case where 1'b0 would not work? What about '0?

Dave


> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
On
> Behalf Of Steven Sharp
> Sent: Thursday, November 01, 2007 12:36 PM
> To: sharp@cadence.com; Eduard.Cerny@synopsys.com;
> john.havlicek@freescale.com; Arturo.Salz@synopsys.com
> Cc: sv-ac@server.eda.org; sv-bc@server.eda.org
> Subject: RE: [sv-ac] Re: [sv-bc] Re: if-else
> 
> 
> >You are correct regarding 0 sized bit vector declarations. However, I
do
> >believe you can use dynamically sized types in integral expressions.
For
> >example:
> >
> >  logic [4:0] b [];	// dynamic array
> >
> >  initial if( b[0] ) ...	// empty integral type
> >
> >I believe in such cases, Verilog treats the empty reference as 'X.
> 
> I believe that this is well-defined, and cannot be used to create an
> zero-width integral value.
> 
> An element of that dynamic array has type "logic [4:0]", even if
> the array contains no elements.  A reference to b[0] in this case is
> an out-of-range array reference, which will produce the default
> initial value for an object of this type, which is 5'bx.  If the
> element type had been "bit [5:0]", the result would have been 6'b0.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
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