[sv-bc] void in an actual expression?

John Havlicek has pointed out the possibility of void members of
tagged unions being used in an expression, and asked about the
meaning of that in a specific context.

We need to figure out the rules for that in general.  Here is John's
original question, and my initial response to it.  Opinions?


>>- Are there any cases where "expression" has no bit at all?  If so,
>>  is sign-extension defined?  I am worried about void members of 
>>  tagged unions and similar things.  Perhaps a tagged union with 
>>  only one member and such that the one member is void type.
>
>There were no such cases in Verilog.  If I had noticed any cases being
>added in SV, I would have raised issues with them.  I didn't notice
>void members of tagged unions.  
>
>There are no rules for how to treat void values in an expression.  A
>void function call in an expression would be illegal.  Therefore, I
>would have to conclude that a reference to a void member of a tagged
>union is not a legal expression, and cannot be used in one.  A tagged
>union with only one member (and thus no need for a tag), and the one
>member being void, would also need to be dealt with.  I would conclude
>that either its declaration is illegal in the first place, or a reference
>to the union as a whole is still considered a void value and is not an
>expression.  Alternately, a void could be considered an expression but
>not of integral type, and therefore unusable in an integral expression.


Steven Sharp
sharp@cadence.com


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