Re: [sv-bc] Re: if-else

From: John Havlicek <john.havlicek_at_.....>
Date: Thu Nov 01 2007 - 09:12:40 PDT
Hi Steven:

Thanks for your clarification.

The only other issues that are nagging me involve stuff that
I guess is near the boundary of the realm of what is useful.  
For example:

- In "expresson != 0", the constant 0 is signed 32-bit.  Are there
  any cases in which we should use 1'b0 instead of 0?

- Are there any cases where "expression" has no bit at all?  If so,
  is sign-extension defined?  I am worried about void members of 
  tagged unions and similar things.  Perhaps a tagged union with 
  only one member and such that the one member is void type.


J.H.

> Date: Thu, 1 Nov 2007 10:51:06 -0400 (EDT)
> From: Steven Sharp <sharp@cadence.com>
> Reply-To: Steven Sharp <sharp@cadence.com>
> Cc: sv-ac@eda.org, sv-bc@eda.org
> Content-MD5: ogJLgUzqnuP7SOfkNcmc3A==
> X-Received: By mx-sanjose.cadence.com as lA1EpoHs026736 at Thu Nov  1 07:51:50 2007
> X-OriginalArrivalTime: 01 Nov 2007 14:55:02.0620 (UTC) FILETIME=[2E8581C0:01C81C97]
> 
> John,
> 
> As you have noted,
> 
> 	if (expression)
> 	
> is equivalent to
> 
> 	if (expression != 0)
> 
> The problem is then that the results of the equality operator are not
> clearly specified when unknowns are involved.  The correct answer is
> that (value1 != value2) is equivalent to (|(value1 ^ value2)).  So for
> (expression != 0), that is equivalent to (|expression), as you have
> suggested.
> 
> This definition makes sense.  If any of the bits are 1, then the value
> is definitely not equal to zero, no matter what any unknown bits are.
> If all of the bits are 0, then the value is definitely equal to zero.
> If the bits are a mixture of 0 and X/Z, then it is unknown whether the
> value is equal to zero.  It depends on the value of the unknown bits.
> 
> After that, there is the issue of how if-else deals with an unknown
> condition.  It rather arbitrarily treats an unknown condition as false.
> Jonathan's suggestion of a cast to "bit" has this same effect.  This
> treatment can cause simulation to produce optimistic results, which is
> undesirable, but that is how it works.
> 	
> Steven Sharp
> sharp@cadence.com
> 

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Received on Thu Nov 1 09:13:19 2007

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