RE: [sv-bc] genvar nesting

What about --
 
genvar i; 
for (i=0; i<5; i=i+1) begin:a 
  genvar i;
  for (i=0; i<5; i=i+1) begin:b 

That is related to

    http://www.eda-stds.org/svdb/view.php?id=930

in which I reported the following --

According to A.1.4, a genvar_declaration is considered a legal
module_or_generate_item_declaration, hence something that can be used in
a generate_block or generate_region.

The intent is not to generate genvars. They are at the same semantic
level as the rest of the generate machinery. For example,
genvar_identifier doesn't accomodate the possibility that the genvar
could be pulled from another generate scope, and the following usage is,
rightly, illegal --

  genvar I, K;

  for (I = 0; I < N; I = I + 1) begin : GEN_I
     genvar J ;
  end

  for (K = 0; K < N; K = K + 1) begin : GEN_K
     for (GEN_I[K].J = 0; GEN_I[K].J < P ; GEN_I[K].J = GEN_I[K].J + 1 )
begin : GEN_J
        ...
     end
   end

Yet I find no text explaining that genvars declared inside a generate
block are not generated, nor talking about their scoping rules.

Also, there are no examples in which a genvar is declared inside a
generate block, except for the "for (genvar ..." examples in the
SystemVerilog LRM.

There seems to be no use anyway for a genvar declaration except to get
the effect of the "for (genvar ..." syntax.

Why not just deprecate the old genvar_declaration syntax in favor of the
cleaner "for (genvar ..." syntax?



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