Summary of Cliff's votes (see attachment for comments) SVDB 909 Yes SVDB 1265 Yes SVDB 1278 No SVDB 1360 Yes SVDB 1487 Yes SVDB 1489 Yes SVDB 1573 Yes SVDB 1610 Yes SVDB 1645 No SVDB 1750 No SVDB 1993 Yes SVDB 2006 Yes SVDB 2029 Yes SVDB 2081 No SVDB 2092 Yes SVDB 2097 Yes SVDB 2102 Yes (Although this restriction is not nearly as useless or cumbersome as the required difference between reg and wire, which also causes users to needlessly change code when moving code back and forth between always and assign ) SVDB 2140 Yes ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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