[sv-bc] Method for detecting connectedness of interface signals

Hi folks,

In writing reusable VIP, we find that it would be useful to be able to tell
whether a signal of a modport (referred to through a virtual interface) is
connected in the design or not. For example, an interface may provide a debug
signal which isn't being used in certain instances of a certain design view.

Vera provided an is_bound() function, but of course, things are different in
SystemVerilog... what would do the trick is to have a way to tell if, in a  modport:
    o There is no driver connected to an input
    o There is no load on an output
    o There is no wire connected to an inout.

Has anyone else run into this need? Any solutions out there?

Thanks,
Mike


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