>From: Gordon Vreugdenhil <gordonv@model.com> >Greg Jaxon wrote: >> Gordon Vreugdenhil wrote: >>> For example given packed >>> unsigned bit vectors "a" and "b", the LRM does not say anything >>> about the precise type of "a[4:5] + b[3:2]". >> >> Are there any dissenters from the idea that this is a packed >> bit or logic vector unsigned [1:0]? > >I don't know. Is this still true for just "a[4:5]"? In effect, >do you *always* normalize? Only for selects and non-simple >expressions? And what about "a[4]"? That is presumably a scalar, not a 1-bit vector. But what about "a[4:4]"? Scalar or vector? Is type'((a)) the same as type'(a), or do the parentheses make it an expression and cause normalization? Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Oct 15 15:22:38 2007
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