Re: Mantis 907 [WAS: RE: [sv-bc] E-mail Ballot: Respond by Oct 14, 2007 8am PDT]

Warmke, Doug wrote:
> 
> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On 
> Behalf Of Stuart Sutherland
> Sent: Friday, October 12, 2007 2:38 PM
> To: 'Maidment, Matthew R'; sv-bc@server.eda.org
> Subject: RE: [sv-bc] E-mail Ballot: Respond by Oct 14, 2007 8am PDT
> 
> I figured I had missed the deadline due to my travel schedule, so I did not
> vote.  If not too late, here's my votes...
> 
>  >
>  > SVDB  907 ___Yes   _X_No 
>  > http://www.eda.org/svdb/view.php?id=907
> 
> I vote NO for four primary reasons. 
> 1) I do not feel this enhancement adds any value to the language.  Are any
> real end-users of SystemVerilog asking for this?  Does the enhancement add
> anything to the language that cannot be done already? 
>  
> DOUG: Yes, real users have asked for this.
> The main point is that this is a way to enforce a "mandatory
> parameter override".  Sometimes there is simply no good default.
> The author of a design unit wants to obligate the client to
> specify the parameter.  This is the way to achieve that modeling goal.
> 

In the Verilog-AMS committee, we also had some interest in "mandatory
parameter overrides," but we had the impression that the Verilog
committees would never let us remove the default from the syntax.

Instead, we created a system task $param_given(identifier) which
returns 1 if the parameter was overidden and 0 otherwise.  This also
helps in some cases where the overriding of a parameter is itself
used to mean something, eg if you specify VTH0 in the BSIM3 model, then
that value is used to set VFB, and otherwise the specified or default
value of VFB is used.  (If you specify both, you get a warning.)

-Geoffrey

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