>From: "Bresticker, Shalom" <shalom.bresticker@intel.com> >5.12 says, > >"An attribute_instance can appear in the SystemVerilog description as a >prefix attached to a declaration, a module item, a statement, or a port >connection. It can appear as a suffix to an operator or a function name >in an expression." > >The syntax in A.8.3 says, > >"inc_or_dec_expression ::= > inc_or_dec_operator { attribute_instance } variable_lvalue > | variable_lvalue { attribute_instance } inc_or_dec_operator" > >The placement of attribute_instance in the last line seems inconsistent >with the text. The text rules were intended to be simple and consistent, but also to guarantee that there was no ambiguity about which item an attribute was attached to. We had the benefit of James Markevitch running the grammar through an automatic parser generator to tell us whether it was ambiguous. The post-increment/decrement operators are different from any of the older operators, since they are unary operators that follow their operand instead of preceeding it. Just following the existing text rules may not ensure that the grammar is unambiguous. It does look to me like it would be OK in this case. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Sep 28 16:11:27 2007
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