RE: [sv-bc] 'inside' on real operands

Would using reals with the inside operator be useful for Verilog-AMS?  If
not, I agree with prohibiting reals as operands of inside.  If the
Verilog-AMS committee sees this as useful, then we should define the
behavior and any caveats.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Jonathan Bromley
> Sent: Monday, September 10, 2007 7:04 AM
> To: Geoffrey.Coram; Alsop, Thomas R
> Cc: Bresticker, Shalom; sv-bc
> Subject: RE: [sv-bc] 'inside' on real operands
> 
> > A "user beware" note in the LRM might be appropriate, but I agree
> > that users should be able to use inside for reals if they want.
> 
> Whilst this makes sense from a language design point of view,
> I think it's very dangerous.  The obvious intuitive interpretation
> of "inside" for reals is "somewhere within this real range". 
> When combined with the fact that wildcard comparison makes no
> sense for reals, and the fragility of == on reals, I think the
> balance should be in favour of prohibiting reals as operands
> of 'inside' if the right-hand operand is considered to be 
> a countable set of values.  Furthermore, if we preserve the
> present meaning of 'inside' whereby its RHS specifies a set
> of values, then a real range such as [1.0:2.0] makes no sense.
> 
> I completely agree with Steven Sharp that the following
> would be both reasonable and (very) useful...
> 
>   R inside {[1.0:2.0], [3.0:4.5]}
> 
> and I think that's what users would expect to be able to
> do - but that makes a specification of a set with an 
> uncountable number of members; and it suggests that 
> putting anything *except* such ranges on the RHS of 
> an 'inside' with real LHS would need to be specified to
> be erroneous.
> -- 
> Jonathan Bromley, Consultant
> 
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