[sv-bc] FW: Doubt regarding string casting in SystemVerilog

I believe Priya is correct, and casting_type should include 'string'.
 
Thanks,
Shalom

________________________________

From: Priya Khanna [mailto:priya@noida.atrenta.com] 
Sent: Monday, September 10, 2007 12:52 PM
To: Bresticker, Shalom
Cc: 'neelu'
Subject: Doubt regarding string casting in SystemVerilog


Hi Shalom, 
 
I have one doubt regarding the casting to string data type as per
LRM1800-2005. 
The section 4.7 of the LRM says -
Casting an integral value to a string variable proceeds in the following
steps:

- If the size (in bits) of the integral value is not a multiple of 8,
the integral value is left extended and

filled with zeros until its bit size is a multiple of 8. The extended
value is then treated the same as a

string literal, where each successive 8 bits represent a character.

- The steps described above for string literal conversion are then
applied to the extended value.

For example:

string s1 = "hello"; // sets s1 to "hello"

bit [11:0] b = 12'ha41;

string s2 = string'(b); // sets s2 to 16'h0a41

i.e we can have the casting done as "string'(b)". However, the formal
syntax defined as per Annex A  does not allow casting to string data
types. 

constant_cast ::=  casting_type ' ( constant_expression )

cast ::= casting_type ' ( expression )   //from A8.4

casting_type ::= simple_type | constant_primary | signing //from A.2.2.1

simple_type ::= integer_type | non_integer_type | ps_type_identifier |
ps_parameter_identifier

Can you please clarify what should be the correct behavior.

Thanks and Regards,

Priya

 

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