RE: [sv-bc] time literals

But ps_identifier allows it.

I think the BNF allows it.

My question is whether there is something in the text/semantics that
disallows it.

Or more generally, where can a time literal be used and not used.

It would seem to have a special data type, but it does not seem to be
defined anywhere.

Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Surya Pratik Saha
> Sent: Thursday, August 30, 2007 4:54 PM
> To: Gran, Alex
> Cc: Bresticker, Shalom; sv-bc
> Subject: Re: [sv-bc] time literals
> 
> Hi Alex,
> realtime declaration is same as real declaration, but not 
> same as real number as defined in BNF. So as per BNF, I don't 
> this this is allowed.
> 
> Regards
> Surya
> 
> 
> 
> -------- Original Message  --------
> Subject: Re:[sv-bc] time literals
> From: Gran, Alex <alex_gran@mentor.com>
> To: Bresticker, Shalom <shalom.bresticker@intel.com>, sv-bc 
> <sv-bc@eda-stds.org>
> Date: Thursday, August 30, 2007 7:16:45 PM
> > From 1800-2008 D3a   (I'm on the road and don't have easy 
> access to my 
> > other LRM versions)
> >  
> >  
> >  
> > A.6.2
> > blocking_assignment ::=
> >
> > variable_lvalue *= *delay_or_event_control expression
> >
> > A.6.5
> >
> > delay_or_event_control ::=
> >
> > delay_control
> >
> > delay_control ::=
> >
> > **
> >
> > *# *delay_value
> >
> > A.2.2.3
> >
> > delay_value ::=
> >
> > unsigned_number
> >
> > | real_number
> >
> > | ps_identifier
> >
> > | time_literal
> >
> >  
> > So, that seems to say value can be any of unsigned_number, 
> > real_number, ps_identifier, time_literal
> >  
> > 6.12
> >  
> >
> > The *realtime *declarations shall be treated synonymously 
> with *real 
> > *declarations and can be used interchangeably.
> >
> > So, as long as data type "real" is expressed as a "real_number"  I 
> > think this is allowed.
> >  
> >  
> > ~Alex
> >  
> >
> > 
> ----------------------------------------------------------------------
> > --
> > *From:* owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org]
> > *On Behalf Of *Bresticker, Shalom
> > *Sent:* Thursday, August 30, 2007 5:26 AM
> > *To:* sv-bc
> > *Subject:* [sv-bc] time literals
> >
> > The following came up in the Verilog-AMS committee.
> > I don't remember whether we discussed this specifically in the past.
> > We certainly discussed closely related issues.
> >
> > Can one write:
> >
> > realtime td = 1.2345ns;
> >
> > # td; // as near a 1.2345ns delay as possible
> >
> > If not, where does the LRM say or at least imply not?
> >
> > Thanks,
> > Shalom
> >
> > Shalom Bresticker
> > Intel Jerusalem LAD DA
> > +972 2 589-6852
> > +972 54 721-1033
> >
> >
> > --
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> 
> 
> 
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