Brad, Many thanks for your helpful response. > In synthesis, access to an interface variable via an interface-type > module port requires that a modport be used and that the > modport impose an 'input' or 'output' direction on the > interface variable to override the default 'ref' semantics. Indeed it does, in 2 of the 3 synthesis tools I can try that understand interfaces. It has been a long time since I tried to use an interface *without* modports in synthesis - but I am sure that at some time in the past I did so, in Synopsys tools, and got away with it. Has this restriction been imposed recently, or is it simply that my memory is deceiving me? Anyway, given all the clarifications from you and others, it's obvious to me that your model of modport inputs and outputs creating continuous assignments is the right one. From the point of view of exposition in the LRM, that also implies that the modport appearing in a module's port list must create a group of variables, one for each input and output member, in the module itself. I'm sorry it has taken so long for the penny to drop with me. However, I humbly suggest that there is some evidence that the LRM needs some clearing-up! And there remains the virtual interfaces problem...... Thanks again to all -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Jul 23 18:28:26 2007
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