[sv-bc] 22.2.2.3 determining port kind

Hi,

22.2.2.3, despite its misnamed title (Aggregate ports), as described
elsewhere, discusses how in a port declaration, the port direction, kind
(net or variable), and data type are determined when not explicitly
specified.

As I understand it, where direction is not specified, then if possible
(without the gory details), its kind and type are inherited from the
previous port declaration.

But if the direction is specified, and if the port kind is not
specified, then:
(a) for input and inout, port kind is wire (default net type)
(b) for output, if data type is specified, port kind is var
(c ) for output, if data type is not specified, port kind is wire

First, did I get that right?

Second, assuming I got that right, or at least the relevant part of it,
the following example seems wrong. (This may have been spotted already,
but just in case...)

// second port inherits its direction and data type from previous port
module mh3 (input byte a, b);
...
endmodule

The second port may inherit its direction from the first, but the first
looks illegal.

It seems to be a net of type byte, but byte is a 2-state type, and thus
a net cannot be byte.

Thanks,
Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6852
+972 54 721-1033


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