Re: [sv-bc] Confusion in function evaluation approach

>From: Greg Jaxon <Greg.Jaxon@synopsys.com>
>
>First, expression evaluation requires producing a temporary
>for everything on the "execution stack" during evaluation.
>Then, each function must be fully evaluated and its result copied
>out into the expression's temp before binding any arguments
>to the next call of f().  If these "automatic" temporaries
>exist it covers a lot of "static" sins.

Minor comment: these temporaries can be static, since they can
be distinct for each value in the expression without needing to
be automatic.


>I feel that is one reasonable approach, although standardizing
>on it would probably leave some vendors in the dust and
>could change memory requirements and even logic for some
>supposedly settled legacy designs.  I'd argue that those
>designs were never actually conforming, but I'd lose the
>argument because so few systems issue warnings in this case.
>
>My gut feeling is that SV ought to break compatibility
>with legacy Verilog and fix this ASAP (but that could
>leave it a starving, jobless, gut if enough legacy code
>uses static functions).  I don't have enough evidence
>one way or the other to make a recommendation, only that
>my early experience with this Verilog "creature feature"
>was that users seldom meant to use static binding, and
>a switch to "infer local latches" was very popular,
>albeit non-standard and a source of sim/synth mismatch.

My limited understanding of synthesis of functions is that it
would essentially inline the calls, which would give the effect
of approach 1.  So if there is legacy code out there that is
doing this, in simulators that use approach 2, then they have
been living with sim/synth mismatches.  Clarifying that approach 1
is required for simulation would solve that.  If this changed the
behavior of any legacy simulations, the result would be finally
finding the cause of sim/synth mismatches that plagued the design.

Steven Sharp
sharp@cadence.com


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