[sv-bc] Is hierarchical reference allowed through modport

Hi,
Is hierarchical reference allowed through modport? Is the following case 
valid?
interface mem_pins_if;
bit       clk, rst;

  modport master_mp( input    clk, rst);

endinterface : mem_pins_if
module top;
 mem_pins_if pins_if();

task run;
forever begin
      @( posedge pins_if.master_mp.clk ); // hierarchical reference 
through modport

end
endtask

LRM is not clear on that.

-- 
Regards
Surya





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