Stu, In Draft 3a, 3.2 starts: 3.2 Design elements A design element is a SystemVerilog module (see Clause 22), program (see Clause 22), interface (see Clause 24), package (see Clause 25), primitive (see Clause 27) or configuration (see Clause 32). These constructs are introduced by the keywords module, program, interface, package, primitive and configuration respectively. The keyword introducing a configuration is "config", not "configuration". Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 17 05:48:43 2007
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